The claimed invention relates to transferring media information and, more particularly, to the distribution of media information across a network.
Various schemes have been proposed for distributing media information (e.g., video data, audio data, video conferencing data, etc.) along communication links. Wireless digital data broadcasting has been proposed for distributing media information among devices in, for example, home entertainment systems. One challenge in playing live streams of media information may be program clock synchronization. For example, a transmitter of the media information may be generating samples at a certain frequency (e.g., typically 48 kHz), which is synchronized to a master program clock (e.g., at 27 MHz Motion Picture Expert Group MPEG-2 System Time Clock). A receiver of the media information should play an identical number of samples per second to avoid buffer overflow or underflows, so it should generate a sample clock with the same frequency as that of the transmitter.
One scheme for such clock synchronization may be for a receiver to use timestamps generated by the transmitter to measure and adjust the difference between its sampling clock frequency and that of the transmitter. This scheme assumes that the communication link between the transmitter and receiver of the media information has a fixed and constant delay for every timestamp.
In carrier sense multiple access collision avoidance (CSMA/CA) networks or carrier sense multiple access collision detection (CSMA/CD) networks, however, the transport delay for packets delivering timestamps may not be constant. In the IEEE 802.11a/b/g-based wireless networks, for example, the transport delay from transmitter to receiver may vary from less than 1 ms to 30 ms or more. The variations in transport delay may be caused by interference from other devices, collisions, retransmissions, changes in signal strength, changes in data rate, and/or other factors. Such variations in transport delay may reduce the effectiveness of timestamp-based clock synchronization schemes.